1. Field of the Invention
The present invention relates to a data and clock recovery circuit in which a distorted data signal transmitted through a communication line can be recovered so as to maintain stable operation not only during normal operating conditions but also when the communication line shorts or when power supply is restored after an outage.
2. Description of the Prior Art
Generally, data and clock recovery circuits are necessarily used in multiplex communication devices which process signals transmitted through communication lines, such as an electronic switching system. As the frequency of the transmitted signals is increased to such a frequency as 155.52 MHz or 622.08 MHz, high speed operation is required for such a data and clock recovery circuit. To maintain the stability of the system, the data and clock recovery circuit also has to maintain stable operation therein even when outside conditions change. Data and clock recovery circuits usually use the phase-locked loop (PLL) method, but because of its characteristics, the circuit can produce a clock with frequency outside of the operating frequency when there is an interruption or a discontinuance of data signal caused by shorting of the communication line or by discontinuance of transmission from the signal source. In worst cases, the operation of a clock itself can discontinue. Also, when there is an accidental power outage or when there is a power shut-off for system maintenance, the clock frequency may not converge to operating frequency and may malfunction after the power is restored because of the characteristics that a PLL circuit has.